Lead Static Timing Analysis Engineer

We are seeking an experienced  Lead STA Engineer  to take ownership of the static timing closure process for complex ASIC / SoC designs. In this role, you will lead timing sign-off activities, coordinate with cross-functional teams, and ensure designs meet performance, power, and area targets while achieving first-pass silicon success.

Key Responsibilities :

• Own and drive  timing closure  for multiple blocks or full-chip designs from synthesis through tape-out.
• Develop and maintain  timing constraints (SDC)  for synthesis, place-and-route, and sign-off flows.
• Perform  setup, hold, recovery, and removal analysis  using industry-standard STA tools.
• Analyze timing reports and debug violations, providing guidance to physical design, RTL, and DFT teams.
• Work closely with clock, power, and signal integrity engineers to address timing and noise-related issues.
• Lead STA reviews with design and physical implementation teams, ensuring issues are tracked and resolved.
• Collaborate with methodology teams to enhance STA flows and timing sign-off quality.
• Contribute to methodology improvements for STA and PNR flows.
• Mentor and guide junior engineers in STA and timing-driven PNR techniques.

Requirements

Must-Have :

Nice-to-Have :