FPGA RTL Design Engineer

Job Summary

We are seeking a talented FPGA RTL Design Engineer to design, implement, and verify digital logic using VHDL / Verilog for FPGA-based systems. The ideal candidate will be responsible for the full FPGA development lifecycle, from architecture design to verification, synthesis, implementation, and lab validation. You’ll work closely with system architects, hardware, and embedded software teams to deliver high-performance and reliable FPGA solutions.

Responsibilities :

Design and implement digital logic using HDLs (VHDL, Verilog)

Develop optimized RTL code for complex FPGA designs, including high speed interfaces, data paths, and control logic.

Perform functional simulation and timing analysis to validate design correctness.

Synthesize and implement FPGA designs using tools like Xilinx Vivado, Intel Quartus, Lattice Diamond, Actel Libero IDE.

Integrate IP cores and develop custom IPs for specific functionality.

Conduct hardware debugging and validation in the lab using logic analyzers, oscilloscopes, and JTAG tools.

Collaborate with PCB designers to define FPGA pin assignments and interface requirements Document design specifications, test plans, and results for internal reviews and compliance.

Participate in design reviews, code reviews, and continuous improvement processes.

Qualifications :

Bachelor’s degree in Electronics / Electrical Engineering.

2+ years of experience in FPGA design and RTL coding.

Strong proficiency in Digital design, RTL coding in VHDL, Verilog.

Experience with FPGA design tools (Vivado, Quartus etc.).

Familiarity with timing closure, floor planning, and constraint management.

Strong proficiency in simulation tools, testbenches, and hardware debugging.

Good understanding of digital logic, finite state machines, bus protocols

Knowledge of SoC FPGA platforms (e.g., Zynq, Stratix 10 SoC).

Strong problem-solving and communication skills