Leadsoc Technologies - FPGA / Silicon Validation Engineer

About the Role :

Own integration and bring-up across FPGA and silicon EVBs for high-speed interfaces (PCIe / Ethernet / DDR4 / DDR5). The role is ~80% system / integration & validation, ~20% RTL design, with board work biased ~80% debug / 20% simple design.

Key Responsibilities

• FPGA Design Flow & Validation : Synthesis, P&R, timing closure (Vivado / Quartus); constraints (XDC / SDC); image generation and lab bring-up.
• RTL (20%) : Targeted Verilog / SystemVerilog changes, glue logic, wrappers, and design-for-debug hooks.
• Interface Bring-up : PCIe, Ethernet, DDR4 / 5 & memory subsystemslink training, calibration, throughput / latency and margining.
• System-level Testing : Develop / execute test plans; corner, stress, and interoperability tests; performance and power characterization.
• Post-Silicon Validation : EVB setup, firmware / driver coordination, silicon feature enablement, errata reproduction and workarounds.
• Debugging : Board-level (oscilloscope, LA, protocol analyzers, JTAG) and design-level (waveforms, assertions, CDC / timing).
• Documentation & Reporting : Clear logs, defect reports, and release / readiness summaries; collaborate with procurement / installation for test assets.

Requirements :

Nice to Have :

30 : 60 : 90 Day Outcomes :

Interview Process :

1) Technical screen (RTL / FPGA / protocols)

2) System & lab debug deep-dive

3) Practical / log-based exercise

4) Managerial fit.

(ref : hirist.tech)