SMTS ASIC Physical design FCL Lead

THE ROLE  :

We are looking for an adaptive, self-motivative design engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The Physical Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

THE PERSON :

Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player.

KEY RESPONSIBLITIES  :

• Handling SOC floorplanning / Partitioning, Die size estimation
• Experience on abutted and non-abutted designs
• Handling of Hierarchical designs (Subfcs), Block partitioning, block pin placement, Feedthrough punching, HFN implementation
• Planning clock Mesh / Tree at SOC / Sub System level
• Full SOC bump planning including GPIO Bump Placement, Pad ring generation / GPIO placement, Hard IP bump placement, GPIO and PG RDL routing
• Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus
• Provide technical support to other teams

P REFERRED EXPERIENCE  :

ACADEMIC CREDENTIALS :

Skills Required

Physical Design