RTL-to-GDSII Implementation Lead

Job Title : Lead Physical Design Engineer

Experience : 7+ Years

Location : Bangalore / Hyderabad

Employment Type : Full-time

Industry : Semiconductors / ASIC / VLSI / SoC Design

Job Summary :

We are seeking a highly experienced and technically strong Lead Physical Design Engineer to drive RTL-to-GDSII implementation for complex SoC or block-level designs. The ideal candidate will lead a team of engineers, oversee physical design execution, and ensure successful signoff and tapeout across advanced process nodes.

Key Responsibilities :

• Own and drive block / full-chip physical implementation from RTL to GDSII.
• Lead floorplanning, placement, clock tree synthesis (CTS), routing, and optimization.
• Guide timing closure, power integrity (IR / EM), DRC / LVS, antenna, and reliability checks.
• Define and execute physical design strategies to meet aggressive PPA targets.
• Interface with cross-functional teams including RTL, STA, DFT, power, and package teams.
• Plan and manage physical design activities for successful project delivery.
• Implement low-power design techniques (multi-VDD, power gating) using UPF / CPF.
• Drive physical design reviews, methodology development, and flow improvements.
• Mentor and guide junior PD engineers;

provide technical leadership and training.

Required Skills and Experience :

Preferred Qualifications :

Interested can share Cv to sharmila.b@acldigital.com