Silicon Implementation Lead

The Role We are seeking an experienced Physical Design Manager to lead SoC / IP implementation on advanced nodes (7nm and below). The role requires strong technical expertise, leadership, and ownership of execution from RTL to GDSII for first-pass silicon success. Key Responsibilities

• Lead end-to-end Physical Design flow (RTL-to-GDSII) for SoCs / IPs.
• Own floorplanning, placement, CTS, routing, STA, IR / EM, and signoff.
• Drive PPA optimisation, ECO closure, and physical verification.
• Collaborate with RTL, verification, architecture, and packaging teams.
• Lead EDA flow automation and scripting for efficiency.
• Mentor and manage a high-performing physical design team. Key Skills & Experience Our USP
• 10+ years in Physical Design with multiple advanced node tapeouts (7nm & below).
• Deep expertise in floorplanning, PnR, STA, low-power (UPF), and signoff.
• Strong knowledge of industry-standard tools (Innovus, PrimeTime, Calibre, Voltus / RedHawk).
• Proficiency in scripting (TCL / Perl / Python) for automation.
• Excellent leadership, communication, and cross-functional skills.