Senior Formal Verification Engineer (CPU)
Experience : 8+ years
Location : Bangalore
Role Overview :
Owns property-based formal verification of the CPU core, pipeline stages, and subcomponents with exhaustive proof goals.
Key Responsibilities :
- Lead formal planning and methodology for control logic, pipelines, and memory subsystems
- Define safety and liveness properties, model check for corner case behavior
- Guide designers in writing formal-friendly RTL and assertions
- Analyze convergence issues, coverage gaps, and create abstraction models
- Integrate formal sign-off into project milestones
Required Skills :
8+ years of formal verification experience with CPUs or processorsStrong with JasperGold, VC Formal, OneSpin or equivalentExpertise in SVA / PSL, abstraction modeling, and formal coverage closureStrong computer architecture background (pipeline, MMU, interrupt logic)Excellent problem-solving, convergence debugging, and documentation skillsInterested,please drop your updated CV to janagaradha.n@acldigital.com