Sr Principal Design Engineer

Description

• RTL Design Engineer for DDR Memory Controller IP development team.
• The role would include the design and support of the RTL of the DDR Memory Controller solution of Cadence. All leading DDR memory protocols will be supported – including DDR4 / LPDDR4.
• The work involved will be working with the existing RTL, the addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring the design is clean for LINT and CDC design guidelines.

Position Requirements :

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