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Job Title : STA Engineer – VLSILocation : BangaloreCompany : TessolveExperience Required : 4+ yearsEducational Qualifications : Bachelor's or Master’s degree in Electrical / Electronics Engineering , VLSI , or related fieldsJob Description : We are seeking a skilled Static Timing Analysis (STA) Engineer with experience in the VLSI domain. The ideal candidate will be responsible for performing and analyzing timing across full-chip and block-level designs, ensuring timing closure across various process-voltage-temperature (PVT) corners.Key Responsibilities : Perform block-level and full-chip STA using industry tools (Primetime, Tempus, etc.)Work closely with physical design (PD) , synthesis , and signoff teams to achieve timing closureAnalyze timing reports, identify violations (setup / hold / DRC), and drive fixesCollaborate with RTL, synthesis, and backend teams to optimize timing pathsHandle timing constraints (SDC), clock definitions, and exceptionsConduct timing ECO analysis and implementationSupport multiple PVT corners, modes, and timing scenariosDebug false paths, multi-cycle paths, and clock domain crossingsEnsure signoff closure with all relevant timing and signal integrity checks️ Required Skills : Strong hands-on experience with Primetime , Tempus , or other STA toolsGood understanding of timing concepts , timing arcs , and delay calculationProficiency in SDC , TCL , and scripting (Perl, Python, etc.)Familiarity with synthesis , place & route , and physical verification flowsExposure to signoff timing closure in advanced nodes (e.g., 7nm, 5nm, etc.)