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Job Title : STA Engineer – VLSI

Location : Bangalore

Company : Tessolve

Experience Required : 4+ years

Educational Qualifications : Bachelor's or Master’s degree in Electrical / Electronics Engineering , VLSI , or related fields

Job Description :

We are seeking a skilled Static Timing Analysis (STA) Engineer with experience in the VLSI domain. The ideal candidate will be responsible for performing and analyzing timing across full-chip and block-level designs, ensuring timing closure across various process-voltage-temperature (PVT) corners.

Key Responsibilities :

Perform block-level and full-chip STA using industry tools (Primetime, Tempus, etc.)

Work closely with physical design (PD) , synthesis , and signoff teams to achieve timing closure

Analyze timing reports, identify violations (setup / hold / DRC), and drive fixes

Collaborate with RTL, synthesis, and backend teams to optimize timing paths

Handle timing constraints (SDC), clock definitions, and exceptions

Conduct timing ECO analysis and implementation

Support multiple PVT corners, modes, and timing scenarios

Debug false paths, multi-cycle paths, and clock domain crossings

Ensure signoff closure with all relevant timing and signal integrity checks

️ Required Skills :

Strong hands-on experience with Primetime , Tempus , or other STA tools

Good understanding of timing concepts , timing arcs , and delay calculation

Proficiency in SDC , TCL , and scripting (Perl, Python, etc.)

Familiarity with synthesis , place & route , and physical verification flows

Exposure to signoff timing closure in advanced nodes (e.g., 7nm, 5nm, etc.)