PMTS Silicon Design Engineer

The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills.

You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc

You are meticulous about Power, Performance and Area while driving schedule and managing cost.

You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide and help to elevate the knowledge and skills of the team around you.

KEY RESPONSIBILITIES :

• RTL to GDS2 flow
• Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC LVS), Crosstalk Analysis, EM / IR
• Working on full chip timing analysis setup and signoff of multi-corner multi-voltage designs.; Hierarchical timing analysis and convergence at block, section and full chip level.
• Engaging closely with Design teams to understand the design, constraints and convergence challenges and providing ECOs with a focus on PPA and TAT optimizations.
• Handling different PNR tools - Synopsys Fusion Compiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk
• Identify and implement opportunities for improving PPA

PREFERRED EXPERIENCE :

Skills Required

Soc, Physical Design, Timing Closure, Perl, Physical Verification, Simulation, Apache