Memory Cell Design Lead

Tata Electronics Private Limited (TEPL) is a greenfield venture of the Tata Group with expertise in manufacturing precision components.

Tata Electronics (a wholly owned subsidiary of Tata Sons Pvt. Ltd.) is building India’s first AI-enabled state-of-the-art Semiconductor Foundry. This facility will produce chips for applications such as power management IC, display drivers, microcontrollers (MCU) and high-performance computing logic, addressing the growing demand in markets such as automotive, computing and data storage, wireless communications and artificial intelligence.

Tata Electronics is a subsidiary of the Tata group. The Tata Group operates in more than 100 countries across six continents, with the mission 'To improve the quality of life of the communities we serve globally, through long term stakeholder value creation based on leadership with Trust.’

Job Summary :

embedded non-volatile memory (eNVM) Bitcell Layout Design Engineer / Lead to join our growing eNVM team & spearhead the development and optimization of eNVM bitcells across wide range of Foundry CMOS technologies from 130nm to 28nm including BCD and advanced FinFET technology nodes. In this position, you are responsible for bitcell design layout and implementation of eNVM bitcells in the memory IPs to build the next generation eNVM products. This role is critical in enabling bitcell for high-yield, high-performance memory IP for a wide range of applications in automotive, IoT, and mobile markets.

Qualifications :

• 5-10 years’ experience in the semiconductor industry
• Bachelor’s, Master’s, or PhD in microelectronics, semiconductor physics or related fields
• Ideally, 5-10 years of experience with an emphasis on memory bit cell and array layout and the characterization of memory bit cells
• Proficient in the use of common EDA tools like Cadence or Calibre for layout design including verification by DRC and LVS etc.
• Basic knowledge of the functionality of memory bit cells and arrays like SRAM, MRAM, RRAM
• Knowledge & good understanding of components included in PDK
• Experience with bench measurement is preferred
• Good understanding of planar & FinFET CMOS flows is preferred

Responsibilities :

Desired Attributes :