RTL Design Integration Manager - FEINT

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Front-End Silicon Design & Integration (FEINT) Manager The role : A Front-End Silicon Design and Integration (FEINT) Manager role in our Security IP (SECIP) development team, where a large number of embedded micro-processor subsystems, hardware accelerators and other IPs vital to improve system performance and functionality are designed and verified. These IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. As a hands-on FEINT manager, you will lead a number of FEINT engineers, work on performing RTL synthesis and PPA (performance, power, area) analysis in order to improve the QoR (quality of result) of RTL designs, creating, adopting and automating RTL static design rule checks, conducting ECO and LEC validations, as well as supporting SOC integration of the IPs. The person : An experienced FEINT engineering leader with strong records of technical leadership and hands-on execution to drive RTL synthesis, PPA analysis, ECO, and static verification tasks to timely completion. A technical mentor and forward-thinking leader who demonstrated strong capability in establishing advanced FEINT methodology and workflow, anticipating / analyzing / resolving technical and planning issues, and enjoyed interacting with team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability. Key responsibilities : Develop, adopt strategy, concept and scripting solutions for RTL synthesis, timing path analysis and PPA analysis at the subsystem level as well as at the block level RTL designs to drive for continued improvement of QoR Develop, adopt ECO strategy, concept and scripting solutions for netlist and / or conformal assisted RTL ECO and LEC validations Develop, adopt strategy, concept and scripting solutions for RTL static design rule checks in collaboration with RTL design team and the corporate methodology team Manage FEINT regression process, create and improve FEINT workflow, processes, and quality metrics, to drive continuous improvement and positive changes Manage IP integration support with SoC team, coordinate resolution of IP integration issues with SoC teams Collaborate with project management and other team leads on FEINT deliverables to the project milestones and on quality metrics Preferred experience : A minimum of equivalent 10 years relevant experience in FEINT engineering. Proven understanding of RTL design, synthesis, and ECO principles Excellent knowledge with FE design tools such as Design / Fusion Compiler, Prime Time, Power Artist, Conformal, Formality, etc. Familiar with VCS / Verdi and SPG based (dynamic / static) verification environments Proficient with Verilog, C / C++ and other scripting languages (e.g. Tcl, Ruby, Perl, Python and Makefile) Excellent skills with Unix / Linux environment Familiar with RTL coding techniques for improved PPA-measured QoR Familiar with RTL coding style for cleanness on design rule checks (LINT, CDC, RDC, etc.) Good understanding of gate level circuit design and physical level design concept and methodology Excellent communication skills (both written and oral) Strong ability to provide mentorship and guidance to junior and senior engineers, a very effective team player, a positive influencer on team morale and culture Prior technical management experience is a plus asset Academic credentials : Major in Electrical Engineering, Computer Engineering, or Computer Science, or possibly a related field Master's Degree preferred Location : Bangalore India #LI-RR1 #LI-Hybrid Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.Front-End Silicon Design & Integration (FEINT) Manager The role : A Front-End Silicon Design and Integration (FEINT) Manager role in our Security IP (SECIP) development team, where a large number of embedded micro-processor subsystems, hardware accelerators and other IPs vital to improve system performance and functionality are designed and verified. These IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. As a hands-on FEINT manager, you will lead a number of FEINT engineers, work on performing RTL synthesis and PPA (performance, power, area) analysis in order to improve the QoR (quality of result) of RTL designs, creating, adopting and automating RTL static design rule checks, conducting ECO and LEC validations, as well as supporting SOC integration of the IPs. The person : An experienced FEINT engineering leader with strong records of technical leadership and hands-on execution to drive RTL synthesis, PPA analysis, ECO, and static verification tasks to timely completion. A technical mentor and forward-thinking leader who demonstrated strong capability in establishing advanced FEINT methodology and workflow, anticipating / analyzing / resolving technical and planning issues, and enjoyed interacting with team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability. Key responsibilities : Develop, adopt strategy, concept and scripting solutions for RTL synthesis, timing path analysis and PPA analysis at the subsystem level as well as at the block level RTL designs to drive for continued improvement of QoR Develop, adopt ECO strategy, concept and scripting solutions for netlist and / or conformal assisted RTL ECO and LEC validations Develop, adopt strategy, concept and scripting solutions for RTL static design rule checks in collaboration with RTL design team and the corporate methodology team Manage FEINT regression process, create and improve FEINT workflow, processes, and quality metrics, to drive continuous improvement and positive changes Manage IP integration support with SoC team, coordinate resolution of IP integration issues with SoC teams Collaborate with project management and other team leads on FEINT deliverables to the project milestones and on quality metrics Preferred experience : A minimum of equivalent 10 years relevant experience in FEINT engineering. Proven understanding of RTL design, synthesis, and ECO principles Excellent knowledge with FE design tools such as Design / Fusion Compiler, Prime Time, Power Artist, Conformal, Formality, etc. Familiar with VCS / Verdi and SPG based (dynamic / static) verification environments Proficient with Verilog, C / C++ and other scripting languages (e.g. Tcl, Ruby, Perl, Python and Makefile) Excellent skills with Unix / Linux environment Familiar with RTL coding techniques for improved PPA-measured QoR Familiar with RTL coding style for cleanness on design rule checks (LINT, CDC, RDC, etc.) Good understanding of gate level circuit design and physical level design concept and methodology Excellent communication skills (both written and oral) Strong ability to provide mentorship and guidance to junior and senior engineers, a very effective team player, a positive influencer on team morale and culture Prior technical management experience is a plus asset Academic credentials : Major in Electrical Engineering, Computer Engineering, or Computer Science, or possibly a related field Master's Degree preferred Location : Bangalore India #LI-RR1 #LI-Hybrid

Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.