RTL -Project Lead.
Experience : 10 to 15 years’ experience.
Educational Qualification : Engineering degree in E&C
Location : Bangalore
Job Description :
- Understand customer’s requirements / specifications.
- Define DSP, System and Board architecture.
- Create proposal for new project enquiries
- Project ownership including identifying risks, dependencies, tracking project schedule, discussions with customers, design reviews.
- Experience in handling the team.
- Involving in Project plan.
- Experience in Microarchitecture
- Partition the algorithms for implementing in FPGA and / or in SW. Identify the building blocks & Signal Processing functions.
- Provide estimates on FPGA resources, computation bandwidth, and memory bandwidth.
- Involving in Project plan
- Create module level details from architecture, coding, simulation and perform peer reviews.
- Define, create and maintain all project related documentation, especially design documents with detailed analysis reports. Provide support to customer during integration phases at test sites and support to production teams
- Creating SRS, ATP for the system
- Apply the methodologies for design, verification or validation
- Provide support to customer during integration phases at test sites
- Defining the architecture of RTL functions, partitioning algorithms
- HDL Coding, review
- Simulation and Implementation
- Testing on board and debugging
- Supervise and mentor at least 2 to 3 DE / SDEs
- Team Management
- Handling multiple projects
Professional Skills :
Proficiency in VHDLXilinx tools for synthesis and implementationThorough understanding of Xilinx FPGA’sFunctional and Timing SimulationHardware Design : Logic Design & Debugging expertiseFPGA Design : VHDL / Verilog RTL Coding, System C / System VerilogFPGA Design : FPGA Synthesis & PAR ToolsFluency, good communication & presentation skills.Configuration / Version control tools like SVN.Knowledge on sRIO, PCIe, Ethernet and other protocols. Desired Skill Set :Implementing DSP algorithms in FPGA environment for Radar and Electronic Warfare systems.Interact with SW and HW teams to define the architecture / system partitioningFPGA development flow : micro-architecting, RTL coding, Synthesis & implementation flow, verification and validation.Modeling the algorithms in Octave / MATLAB, generating testvectors, visualizing data.
Converting floating point modules to FPGA friendly fixed point modules.Familiarity with DSP Xilinx IP cores and customization options : FFT, FIR, DDC, NCO etc.,Thorough knowledge on interfacing with ADCs and DACs and interpreting their performance.Basic skills on project management and tools like MPPTransferring data from FPGA over sRIO, PCIe, Ethernet and other protocols.Configuration / Version control tools like SV