Principal Engineer Mixed Signal Verification

Candidate should have working experience with AMS Verification on multiple SOC's or sub-systems. One should have proficiency in AMS simulation environment using Cadence / Synopsys / Mentor tools. Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development / modifications from mixed signal perspective is a plus. Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Working knowledge of Perl / Skill / Python / Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment.

Job Description

In your new role you will :

• Behavioral modeling : Verilog, Wreal or SV-RNM -Full
• AMS Verification for SoC or IPs -Full
• Test plan preparation as per the dynamics of product specifications - Full
• Dealing challenges with AMS methodologies of Cadence : irun / xrun or Synopsys : XA-VCS or Mentor Eldo ADMS -partial
• Testcase Debug & proposing new scenarios - Partial
• Handling project dynamics on scope, schedule and effort – coming up with alternative verification plans, Mentoring Junior engineer – Partial
• Ability to lead MSV projects independently
• Drive enhancements in known methodologies

Your Profile

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Skills Required

Verilog Hdl, Uvm, Spectre, Perl, Python, Tcl