Semiconductor Packaging Engineer

Job Descriptions – Package designer / Allegro Package Designer

• 5+ years in IC package design and development with proficiency with Cadence Allegro Package Designer.
• Netlist creation, BGA creation as per the inputs Conduct feasibility studies to advise optimum pad layout, interconnect types and substrate parameters for a specific IC device or application.
• Define substrate stack-ups, routing strategies and via structures. Substrate design experience for RF, digital, high-speed and mixed signal ie Excellent understanding of SI / PI requirement for routing HSIO (DDR, SERDES, etc).
• Good experience in UCIE-Advanced and Standard technology, HBM technology. Experience in setting design rule checks (DRC) to ensure layouts meet specific manufacturing, Assembly and design guidelines.
• Experience of optimise the die breakout for signals and create patterns for High power. Strong understanding of HDI substrate technologies, layout design rules, and materials for optimal performance.
• Verify designs against electrical, thermal, mechanical, and manufacturability requirements. Knowledge on different Package types.
• Experience in Wire bond, Flip chip Substrate designs. Hands on experience with Wire bond, Flip chip & advanced packaging technologies (2.5D, 3D, RDL, embedded passives, etc.)
• Strong experience with CoWoS (Chip-on-Wafer-on-Substrate) interposer design and the impact of the substrate design to support CoWoS.
• Knowledge of different OSAT design rules