3–8 years of experience in Memory or Custom Layout DesignStrong understanding of memory architectures and layout optimization techniquesHands-on experience with FinFET technology and DRC rulesProficient in physical verification flows (DRC, LVS, ERC) and debuggingExperience with EM / IR analysis and fixesSkilled in Cadence Virtuoso and Calibre toolsFamiliarity with scripting languages for automation and flow customizationBachelor's degree (B.E / B.Tech) in Engineering or related fieldSkills Required
Hardware Design, Signal Integrity, Pcb Layout, FPGA Design, Verification Tools