Lead SerDes Verification Architect

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PMTS SILICON DESIGN ENGINEER

As a SerDes Verification Architect , you will be responsible for the verification and validation of high-speed SerDes interfaces, including testing data integrity, performance, and protocol compliance. You will work closely with hardware and design teams to ensure that SerDes designs meet the required specifications, operating parameters, and quality standards.

Key Responsibilities :

• Verification of SerDes Designs : Develop and execute verification plans and testbenches for SerDes IPs (Intellectual Property) and subsystems to ensure they meet functional and performance requirements.
• Testbench Development : Design and implement verification testbenches using industry-standard verification methodologies (e.g., UVM, SystemVerilog, VHDL).
• Simulation and Debugging : Perform simulations, analyze results, and debug issues related to timing, protocol errors, and other design anomalies in SerDes blocks.
• Performance Evaluation : Evaluate and validate performance characteristics of SerDes systems including jitter, bit error rates (BER), signal integrity, eye diagrams, and other key metrics.
• Protocol Compliance Testing : Verify adherence to relevant SerDes protocols such as UCIe , PCIe, Ethernet, USB, DDR, DisplayPort, or custom protocols.
• Automated Testing : Develop automated regression tests to ensure the robustness and stability of the SerDes design over multiple versions and iterations.
• Collaboration : Work closely with the design, hardware, and software teams to troubleshoot issues, implement fixes, and verify design changes.
• Documentation : Create detailed reports and documentation on verification results, test scenarios, and issues found during testing.
• Verification methodology : Provide feedback for design and verification process improvements and contribute to innovation in verification strategies and methodologies.
• Experience :

16+ years of experience in SerDes verification or high-speed communication verification.

Preferred Skills :

Exposure to high-speed memory interface design and verification, including DDR controller IP verification.

Functional coverage, assertions knowledge in SV / UVM.

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Benefits offered are described : .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

Skills Required

systemverilog, Uvm, jitter, Usb, displayport , Vhdl, Signal Integrity, Ethernet, Python, Pcie, Perl, Ddr