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Physical Design- CDC RDC Lead

Physical Design- CDC RDC Lead

ConfidentialBengaluru / Bangalore
30+ days ago
Job description

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites /  timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Key Responsibilities :

  • Physical Design Implementation :
  • Translate complex CDNA and RDNA graphics IP RTL designs into optimized physical layouts.
  • Utilize industry-leading EDA tools for synthesis, place-and-route (PnR), and physical verification processes to take the design thru mock-taepout
  • Performance Optimization :
  • Focus on power, performance, and area (PPA) optimization to meet the stringent requirements of high-performance graphics and compute products.
  • Collaborate with architecture and front-end design teams to align RTL design with physical constraints and objectives.
  • Verification and Timing Closure :
  • Conduct static timing analysis (STA) to ensure robust timing closure and sign-off for graphics IP.
  • Implement and verify design rule checks (DRC), layout versus schematic checks (LVS), and power grid analysis tailored to CDNA and RDNA requirements.
  • Collaboration and Communication :
  • Work closely with cross-functional teams, including architects, RTL designers, and verification engineers to ensure seamless integration and functionality of graphics IP cores.
  • Provide feedback and suggest improvements to design methodologies and processes to push the technology envelope further.
  • Documentation and Reporting :
  • Maintain comprehensive design documentation, methodologies, and updates.
  • Prepare detailed reports on design progress, performance metrics, and any technical challenges encountered.

PREFERRED EXPERIENCE :

  • Domain Expertise :
  • Experience with working on complex design and optimizing for performance, power, and area.
  • Technical Proficiency :
  • Proven track record in RTL synthesis, place-and-route (PnR), and static timing analysis (STA) for complex IP cores.
  • Proficiency with industry-leading EDA tools, such as Synopsys Design Compiler, Cadence Innovus, and timing analysis tools like PrimeTime.
  • Experience with low-power design methodologies and techniques for high-performance graphics IP.
  • Design and Verification :
  • Successful completion of full-chip sign-off, including design rule checks (DRC) and layout versus schematic (LVS) checks.
  • Strong skills in signal integrity analysis, including crosstalk and IR drop evaluations.
  • Process Technology :
  • Experience working with advanced semiconductor process nodes (e.g., 7nm, 5nm, or below).
  • Knowledge of process-related challenges and optimization techniques for graphics applications.
  • Scripting and Automation :
  • Proficiency in scripting languages such as Perl, Python, or TCL to automate design flows and improve efficiency.
  • Experience developing and maintaining scripts for design rule checks and optimization processes.
  • Problem-Solving and Innovation :
  • Demonstrated ability to solve complex design challenges using innovative approaches.
  • A track record of contributing to the improvement of design techniques and methodologies in a graphics-focused engineering team.
  • Skills Required

    Sta, PNR, cdc, Digital Design

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