Principal RTL Design Engineer

Principal / Staff IP / RTL Design Engineer (AI Accelerator) – Multiple positions - Hyderabad

Hyderabad / Bangalore

Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad / Bangalore

Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market.

Well-funded product startup is looking for RTL Design Engineers to contribute to the development of novel high performance AI accelerators from scratch. In this role you will collaborate with cross-functional teams, including architect, software, verification, physical design, systems engineers, to define and implement next generation AI architectures.

We are seeking highly experienced individuals who have a passion for innovation and are excited about the opportunity to create world class products from India. The key responsibilities for this role include, but are not limited to :

Key Responsibilities

• Design and implement high-performance TPUs / MPUs and other related AI blocks using RTL.
• Own IP / block-level RTL from spec to GDS, including design, synthesis, and timing closure.
• Optimize design for power, performance, and area (PPA).
• Interface with physical design and DFT (Design for Test) engineers for seamless integration.
• Drive design reviews, write design documentation, and support post silicon bring-up / debug.

Minimum Qualifications

Contact : Uday

Mulya Technologies

muday_bhaskar@yahoo.com

"Mining The Knowledge Community"