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Principal IP / RTL Design Engineer (AI Accelerator)

Principal IP / RTL Design Engineer (AI Accelerator)

Mulya TechnologiesGreater Hyderabad Area, India
30+ days ago
Job description

Principal / Staff IP / RTL Design Engineer (AI Accelerator) – Multiple positions - Hyderabad

Hyderabad / Bangalore

Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad / Bangalore

Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market.

Well-funded product startup is looking for RTL Design Engineers to contribute to the development of novel high performance AI accelerators from scratch. In this role you will collaborate with cross-functional teams, including architect, software, verification, physical design, systems engineers, to define and implement next generation AI architectures.

We are seeking highly experienced individuals who have a passion for innovation and are excited about the opportunity to create world class products from India. The key responsibilities for this role include, but are not limited to :

Key Responsibilities

  • Design and implement high-performance TPUs / MPUs and other related AI blocks using RTL.
  • Own IP / block-level RTL from spec to GDS, including design, synthesis, and timing closure.
  • Optimize design for power, performance, and area (PPA).
  • Interface with physical design and DFT (Design for Test) engineers for seamless integration.
  • Drive design reviews, write design documentation, and support post silicon bring-up / debug.

Minimum Qualifications

  • B.S. / M.S. / Ph.D. in ECE / CS from top engineering college with 5-15 years of related experience.
  • Previous experience in either high performance processor design or AI accelerator design is plus.
  • Clear understanding of floating-point arithmetic, vector processing, SIMD, MIMD, VLIW, EPIC concepts.
  • Strong grasp of digital design fundamentals, computer architecture, virtual memory and high-speed data-path design.
  • Proficiency in Verilog / SystemVerilog and simulation tools.
  • Experience with EDA tools (e.g., Synopsys, Cadence) for synthesis, lint, CDC, and timing analysis.

    • Contact : Uday

    Mulya Technologies

    muday_bhaskar@yahoo.com

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    Principal Ai Engineer • Greater Hyderabad Area, India