Minimum Qualifications :
- Bachelor's degree in Computer Science, Electrical / Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
- OR
- Master's degree in Computer Science, Electrical / Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
- OR
- PhD in Computer Science, Electrical / Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
Preferred Qualifications :
Bachelors or Master's degree in Computer Science, Electrical / Electronics Engineering, Engineering5+ years of Hardware Engineering or related work experience.1+ year in a technical leadership role with or without direct reports.Principal Duties and Responsibilities :
5-7 years of relevant experience in ASIC Physical VerificationGood understanding of overall design Flow from RTL to GDS.Hands on Experience on Physical Verification closure of full chip & Hierarchical DesignsHands on DRC & LVS Experience on Lower node Technologies with Synopsys / Cadence / Calibre ToolsGood knowledge on PnR flow, ECO implementationKnowledge on Perl / TCL scripting language , SVRF coding is advantageExperience on multi voltage designsGood understanding of other domains of signoff of in Physical Design (STA / PV / IR / FV / CLP)Responsibilities
Responsible for Block / Chip Tile PV closure to achieve the best PPADRC & LVS closure for Block and Full Chip for complex hierarchical Designs in 4nm / 3nm nodesInteraction with IR, IP , ESD & PD teams for Physical Verification Convergence & Resolving ConflictsAble to work on multiple blocks at same time with minimal supervisionResponsible for Full Chip LVS & DRC closureResponsible for Analog integration closure for all IP's used in SOCSkills Required
Electronics Engineering, Computer Science, Electrical Engineering, Asic Physical Design, Tcl Scripting, Physical Design