RTL Design(Video)-Sr Engineer

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group >

Hardware Engineering

General Summary

• 2-5 years of hardware experience involving design and integration of large complex Sub-systems / SoCs.
• Strong DSP / Multimedia Domain Knowledge on Video Codecs / Computer Vision / AI / ML Hardware Architecture is preferred.
• Experience in micro-architecting & designing complex datapath cores for ASICs / SoCs including AI / ML cores for CV applications
• Experience with RTL coding using Verilog / VHDL / system Verilog
• Should have knowledge of AMBA protocols - AXI, AHB, APB, with clocking / reset / debug architectures.
• Hands on experience in Low power design is required
• Hands on experience in Multi Clock designs, Asynchronous interfaces is required
• Experience in ASIC development flow such as Lint, CDC, Synthesis and CLP is required.
• Understanding of constraint development and timing closure is a plus.
• Experience in Synthesis / Functional ECOs / Understanding of timing concepts is a plus.
• Work closely with the verification and validation teams for pre / post Silicon debug
• Excellent oral and written communications skills
• Proactive, creative, motivated to learn and having good collaborative skills.

Minimum Qualifications

OR

Master's degree in Computer Science, Electrical / Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical / Electronics Engineering, Engineering, or related field.

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Skills Required

low power design, LINT, cdc, Clp, Timing Closure, Synthesis, Vhdl, Verilog, RTL Coding, Video Codecs, System Verilog, silicon debug, Axi, APB, AHB, Timing Concepts, Computer Vision