Senior Engineer Digital Functional Verification

Job Description

In your new role you will :

• create and define verification plans;
• develop verification environments for our ICs using UniversalVerification Methodology (UVM).
• draw on test scenarios using SystemVerilog;
• verify functionality using the Constrained Random approach;
• develop assertions in SystemVerilog for formal verification;
• Interact with other disciplines, such as Concept and ApplicationEngineering, to define verification plans and strategies;
• provide proactive support to users of our verification flowenvironment;
• be responsible for our verification methods;

Your Profile

You are best equipped for this task if you have :

Contact : [HIDDEN TEXT]

#WeAreIn for driving decarbonization and digitalization.

As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.

Are you in

We are on a journey to create the best Infineon for everyone.

This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills.

Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.

Click here for more information about Diversity & Inclusion at Infineon.

Skills Required

Vhdl, systemverilog