Senior Design Verification Engineer

M.Tech + 1 year of relevant industry experience in Analog Domain OR 2+ years of experience in AMS Verification Strong fundamentals in mixed-signal designs, including a thorough understanding of analog building blocks Writing and maintaining Analog Mixed Signal models, using real number modelling and VerilogAMS. Experience with Cadence Mixed-Signal Design Environment tools, including Virtuoso, ADE Assembler, Xcelium - Expertise in verifying ADCs, DACs, PLLs, and mixed-signal blocks Expertise in mixed-signal waveform review, debugging, and coverage analysis. Candidate should have test bench development experience.