GPU Functional Verification Engineer

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group >

Hardware Engineering

General Summary

Qualcomm is a company of inventors that unlocked 5G, ushering in an age of rapid acceleration in connectivity and new possibilities. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform its potential into world-changing technologies and products.

In the role of GPU Functional Verification Engineer , your project responsibilities will include the following,

• Develop deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces
• Strategize, brainstorm, and propose a DV environment, develop test bench, own test plan, debug all RTL artefacts, and achieve all signoff matrices
• Engage with EDA vendors, explore new and innovative DV methodologies to push the limits of sign off quality
• Collaborate with worldwide architecture, design, and systems teams to achieve all project goals

urrently, we are looking for candidates who can match one or more of the profiles listed below,

Strong knowledge of UVM based System Verilog TB Knowledge of GPU pipeline design is a plus, not mandatory Proficiency with formal tools – working knowledge of Property based FV is a plus, not mandatory Strong communication skills (both written and verbal) Most importantly, ability to learn, improve and deliver

Experience

Education Requirements

Selected candidates will be part of the GPU HW team which is passionate about developing and delivering the best GPU Cores for all Qualcomm Snapdragon SOC products. Qualcomm GPU is an industry-leading solution which is driving the benchmarks in mobile computing industry and the future of mobile AR / VR.

The pre-Si verification team in Bangalore is currently heavily involved in the following

Minimum Qualifications

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If you would like more information about this role, please contact Qualcomm Careers.

Skills Required

Perl, Uvm, System Verilog, Python