Principal Verification Engineer (VLSI Verification + AV +AI Expertise)

Principal Staff Verification Engineer (VLSI Verification + AV +AI Expertise)

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Thu, Aug 21 at 4 : 49 PM

Job Description – Staff Verification Engineer (VLSI Verification + AV +AI Expertise)

Position : Staff Verification Engineer – VLSI Verification Lead

Location : Hyderabad

Experience : 12+ years in Functional Verification

Key Protocol Experience : MIPI DSI, DisplayPort, HDMI

Role Overview

We are seeking a highly skilled Staff Verification Engineer with strong expertise in VLSI functional verification and a good understanding of AI model deployment for Audio / Video applications. The candidate will lead verification efforts for complex SoCs / IPs, while also collaborating with cross-functional teams on next-generation multimedia and AI-driven system use cases.

Requirements

Experience : 12+ years in functional verification; minimum 5+ years in Multimedia (Display, Camera, Video, Graphics) domain .

Domain Expertise :

Strong knowledge in Display (Pixel processing, composition, compression, MIPI DSI, DisplayPort, HDMI) and Bus / Interconnect (AHB, AXI).

Multimedia technologies : Audio / Video codecs, Image Processing, SoC system use cases (Display, Camera, Video, Graphics).

Good understanding of DSP, codecs (audio / video), and real-time streaming pipelines.

AI accelerators – architecture understanding, verification, and deployment experience across NPUs, GPUs, and custom AI engines.

SoC system-level verification with embedded RISC / DSP processors.

AI / ML Skills :

Experience with AI models (ex. CNN ) and statistical modeling techniques.

Exposure to audio frameworks, audio solutions, and embedded platforms.

Hands-on in multimedia use cases verification and system-level scenarios.

Strong exposure to MIPI DSI-2, CSI-2, MIPI D-PHY, C-PHY.

Verification Expertise :

Proven expertise in developing / maintaining SystemVerilog / UVM-based testbenches, UVCs, sequences, checkers, coverage models.

Strong understanding of OOP concepts in verification.

HVL : SystemVerilog (UVM), SystemC (preferred).

HDL : Verilog, SystemVerilog.

Leadership & Collaboration :

Mentor and guide junior verification engineers; drive closure for IP and SoC-level deliverables.

Strong written and verbal communication skills; ability to convey complex technical concepts.

Proven ability to plan, prioritize, and execute effectively.

Debugging & Architecture Knowledge :

Excellent debug skills across SoC architecture, VIP integration, and verification flows.

Responsibilities

AI & Multimedia (AV) Responsibilities

Develop, optimize, and deploy AI models for audio and video applications, with strong focus on inference efficiency and performance optimization across NPUs, GPUs, and CPUs.

Perform model evaluation, quantization, and compression to enable fast and robust inference on embedded hardware.

Collaborate with cross-functional R&D, systems, and integration teams for system use case verification and commercialization support.

Evaluate system performance, debug, and optimize for robustness and efficiency.

Participate in industry benchmarking and trend analysis; introduce state-of-the-art architectural and technical innovations.

ASIC / SoC Verification Responsibilities

Lead and contribute to feature, core, and subsystem verification during ASIC design and development phases through RTL and Gate-Level simulations.

Collaborate with the design team to define verification requirements, ensuring functional, performance, and power correctness.

Develop and execute comprehensive test plans and drive verification closure.

Create and maintain SystemVerilog / UVM testbenches, assertions, and functional coverage models.

Implement and enhance automation flows to improve verification efficiency.

Participate in debug activities throughout the development cycle.

Apply ASIC expertise to define, model, optimize, verify, and validate IP (block / SoC) development for high-performance, low-power products.

Collaborate with software and hardware architecture teams to develop strategies meeting system-level requirements.

Evaluate complete design flows from RTL through synthesis, place-and-route, timing, and power usage.

Write detailed technical documentation for verification methodologies, flows, and deliverables.

Contact : Uday Bhaskar

Mulya Technologies

"Mining the Knowledge Community"

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