Required Skills & Experience :
- 8+ years of experience in ASIC / DFT design, simulation, and silicon validation.
- Proven experience in at least one full-chip DFT implementation cycle from concept to silicon.
- Strong knowledge of DFT methodologies, including scan insertion, compression, ATPG, MBIST, and boundary scan (JTAG).
- Hands-on experience with the following tools :
1. ATPG : TestKompress
2. MBIST : MentorETVerify (or equivalent MBIST tools)
3. Simulation : VCS (preferred), ModelSim
Good understanding of ASIC design flow, synthesis, timing analysis, and verification concepts.Experience with post-silicon debug and yield analysis.Proficiency in scripting (Tcl, Perl, Python, or Shell) for Qualifications :Familiarity with Logic BIST implementation.Experience in high-volume manufacturing test program bring-up.Knowledge of low-power DFT methodologies.Strong analytical, problem-solving, and debugging skills.Soft Skills :
Excellent communication and collaboration abilities.Strong attention to detail and quality-oriented mindset.Ability to work in a fast-paced, cross-functional environment.(ref : hirist.tech)