Block-level and sub-system DFT micro-architecture including SCAN, MBIST, IP tests, JTAG
Develop and execute test insertion flow for scan, MBIST, JTAG
Estimate and achieve targeted test coverage.
Run RTL and gate-level simulation for all DFT modes.
Develop and debug timing constraints for all DFT modes.
Verify test patterns pre-silicon and post-silicon
Write scripts in TCL and Perl to achieve productivity enhancements through automation.
Required Background :
In-depth knowledge of VLSI design as well as hardware description languages such as Verilog.
Experience with complex block-level and SOC-level DFT execution in advanced finFET technology.
Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent.
Good problem solving and debug capabilities is a preferred plus.
Good knowledge of hardware simulation tools like VCS, Verdi, etc.
Proficient in scripting languages Should be proficient at working with cross functional and cross site teams.
Must possess good communication skills, be a self-driven individual and a good team player.
Personal Attributes :
Can-do attitude.
Strong team player.
Curious, creative, and good at solving problems.
Execution and results oriented. Self-driven, Thinks Big and is highly accountable.
Good communication skills.
(ref : hirist.tech)
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Senior Dft Engineer • Bengaluru,Karnataka,India
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