Principal Design Verification Engineer - CXL / PCIe

Principal Design Verification Engineer - CXL / PCIe

Bangalore

About company

Top40 Semiconductor Organization in the world

We are seeking talented Design Verification Engineers with proven expertise in industry-standard protocols such as PCIe, Ethernet and CXL. You will play a key role in the functional verification of designs, from developing block-level and system-level verification plans to writing test sequences, executing tests, and collecting and closing coverage.

Responsibilities :

• Develop and execute block-level and system-level verification plans.
• Write and execute test sequences and collect and close coverage.
• Collaborate with RTL designers to debug failures and refine verification processes.
• Utilize coding and protocol expertise to contribute to functional verification.
• Develop user-controlled random constraints in transaction-based verification methodologies.
• Write assertions, cover properties, and analyze coverage data.
• Create VIP abstraction layers for sequences to simplify and scale verification deployments.

Basic Qualifications :

Required Experience :

Preferred Experience :

Contact : Uday

Mulya Technologies

muday_bhaskar@yahoo.com