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Only 24h Left : Principal RTL Design Engineer
ACL DigitalIndia7 hours ago
Job descriptionBTech, MTech in ECE / EE 10+ years hands-on experience in microarchitecture and RTL development Proficiency in developing micro-architecture from the design requirements, defining the H / W- S / W interface In-depth understanding of MIPI CSI and DSI protocols Experience designing IP blocks for video and audio chips Proficiency in Verilog, System Verilog Familiarity with industry-standard EDA tools and methodologies Experience with large high-speed, pipelined, and low power designs Excellent problem-solving skills and attention to detail Strong communication and collaboration skills Experience with modern programming languages like Python is a plus
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Only 24H Left Design • India
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