Job Description :
We are looking for a skilled DFT Verification Engineer with hands-on experience in DDR IP or subsystem-level verification to join our growing team in Bangalore. The ideal candidate will be responsible for generating silicon test patterns for DDR interfaces using JTAG and performing thorough gate-level simulations for verification.
Key Responsibilities :
Develop and verify DFT patterns for DDR interfaces using JTAG-based test methodologies.
Perform gate-level simulations (GLS) for validating DDR test patterns and ensure design correctness at silicon level.
Collaborate with SoC / IP design, DFT, and validation teams to resolve issues. Debug simulation mismatches and improve test coverage and pattern quality.
Participate in timing-aware verification processes at gate level.
Required Skills :
4–9 years of experience in DFT verification, specifically in DDR interface or subsystem.
Strong knowledge of DDR protocols (DDR3 / DDR4 / LPDDR4 / LPDDR5).
Proficiency in gate-level simulations and debugging.
Familiarity with JTAG-based testing and silicon validation flows.
Hands-on experience with Verilog / VHDL, DFT tools, and simulation tools like VCS, NC-Sim, or ModelSim.
Preferred Qualifications :
Prior experience in working with semiconductor IPs or SoCs.
Exposure to timing-aware DFT simulation environments.
Strong scripting knowledge (TCL / Perl / Python) for automation.
Mail : [HIDDEN TEXT]
Contact : 7729881999
Education
Master of Public Administration (MPA), PGP, Master of Library & Information Science (MLIS), Bachelor of Business Administration (B.B.A), Bachelor Of Computer Application (B.C.A), Masters in Technology (M.Tech / M.E), Master in Computer Application (M.C.A), Post Graduate Programme in Management for Executives (PGPX), Master OF Business Administration (M.B.A), Doctor of Business Administration (DBA), Bachelor Of Technology (B.Tech / B.E), Post Graduate Diploma in Computer Applications (PGDCA), PGDM
Skills Required
Vcs, Python, Tcl, Modelsim
Verification Engineer • Bengaluru / Bangalore