Job description
- The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
- Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
- The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success
- Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
- You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day.
Job Summary :
We have an immediate opening in the Post Silicon Physical Layer Electrical Validation team at Cadence Design Systems Bangalore, for the post of 'Design Engineering Manager'.The responsibility entails leading pre silicon Physical Layer Electrical Validation infrastructure development as well as post silicon validation efforts primarily on Cadences High Speed SERDES Test chips, ie, activities involving (but not limited to) designing the hardware and software architecture required to test the test chips (be it the test PCBs, controlling FPGA platforms, Labview / python automation for controlling the HW etc), defining test plans for rigorously testing the compliance of the Test chips to the Physical Layer Electrical specifications , implementing these tests as planned, generating high quality test reports based on the test results etc.What we are looking for in potential candidates is listed below.
Minimum Qualifications :
6-10 years (with Btech) or 4-8 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical ValidationDeep Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO etcStrong hands on Experience in using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etcPreferred Qualifications :
Experience managing small teams (at least 2 members and above)Experience leading the complete post silicon validation efforts for at least one full project1-2 years of experience in FPGA Design, PCB schematic and layout design & PrototypingPre-Silicon IP / SoC Physical Layer Electrical Validation experience related to board bring-up & Debug.Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C / C++, TCLExperience conducting hiring interviews and mentoring new hiresCandidates are expected to be passionate about analog and digital electronic circuit design aspects as well as signal processing related aspects.Role : Engineering Manager
Industry Type : IT Services & Consulting
Department : Engineering - Software & QA
Employment Type : Full Time, Permanent
Role Category : Software Development
Education
UG : B.Tech / B.E. in Any Specialization
PG : M.Tech in Any Specialization
Key Skills
C++ Automation USB FPGA SOC Verilog Ethernet PCIE Automotive Python
Skills Required
Software Developer, C C++, Python