STA Engineer (15h Left)

Job Summary :

We are seeking a skilled STA Engineer with a strong background in Test and DFT architectures. The ideal candidate will have hands-on experience evaluating and writing high-quality timing constraints (SDCs) and performing thorough timing checks across complex digital designs.

Key Responsibilities :

• Analyze and validate timing constraints (SDC) for DFT architectures.
• Develop and maintain accurate SDC files to support timing closure.
• Collaborate with design and test teams to ensure timing integrity across scan, BIST, and other test modes.
• Perform timing checks and quality assessments to identify and resolve constraint-related issues.
• Contribute to the development of best practices for DFT timing constraint generation and validation.

Required Qualifications :

Preferred Qualifications :