Senior STA Engineer

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The V erification Engineering team furthers and encourages continuous technical innovation to showcase successes as we'll as facilitate continuous career development.

THE PERSON :

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites /  time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES :

• we'll versed with timing signoff methodology and corner definitions
• Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks
• Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts)
• Responsible for Timing closure of one or multiple sub chip / subsystem OR Full chip.
• Ensuring block / SS level Interface timing closure along DRV closure
• Generating timing ECO using tools DMSA / Tweaker and leading subsystem / Subchip / FC timing closure

PREFERRED EXPERIENCE :

Ghz range )

ACADEMIC CREDENTIALS :

Skills Required

Sta