SoC RTL Design Engineer

Description :

We are seeking an experienced SoC RTL Design Engineer with strong expertise in IP and subsystem design, RTL development, and SoC-level integration. The ideal candidate will have deep knowledge of RTL quality methodologies, AMBA protocols, timing concepts, and industry-standard design tools. The role requires collaboration across design, verification, physical design, DFT, and firmware teams to deliver high-quality, production-ready SoC designs.

Key Responsibilities :

IP / Subsystem / SoC Architecture & Design :

• Lead and contribute to IP, subsystem / cluster, and SoC-level RTL design using Verilog / SystemVerilog.
• Analyze architectural requirements and translate them into efficient, synthesizable RTL.
• Drive subsystem integration, ensuring compatibility across interfaces and seamless connectivity within the SoC.

RTL Quality & Methodology :

Synthesis, Low Power & Timing :

Interface Protocols & Bus Architecture :

Automation & Scripting :

Required Skills & Qualifications :

Preferred Qualifications :

(ref : hirist.tech)