Principal Verification Engineer

Design Verification :

• B.E / B. Tech / M.E / M. Tech in electronics with 7-10+ year experience in verification domain.
• Own or lead verification of complex flows at the SOC, subsystem, or IP levels.
• Plan the verification of complex design IP / SoC interacting with the architecture and design engineers to identify verification test scenarios.
• A solid understanding of memory protocols such as DDR, LPDDR, or HBM.
• Prior work on UFS (Universal Flash Storage),Ethernet and PCIe Protocol is desirable.
• Good understanding of processor based Soc level verification which includes native ,Verilog ,system Verilog and UVM mix environment.
• Hand on experience with verification tools such as VCS, waveform analyzer and third party VIP integration (such as Synopsys VIPs).
• Hands on experience in UVM. C / C++ ,System Verilog verification language.
• Good understanding of AXI-AMBA protocol variants.
• Can work with scripting language (shell, Makefile, Perl)
• Strong understanding of design concepts and ASIC flow.
• Good problem solving, analytical and debugging skill is must.