FPGA Design Intern

Key Responsibilities

• 0–1 years of hands-on experience in implementing designs on FPGA
• Strong expertise in RTL coding using VHDL / Verilog / System Verilog
• Understanding of FPGA design flow including constraint definition, synthesis, floor planning, place & route, and timing closure
• Create block-level design documentation
• Write testbenches and sequences in SystemVerilog
• Work with lab equipment for validation and testing
• Familiarity with standard interface protocols (e.g., SPI, I2C, UART, etc.)
• Knowledge of modern FPGA architectures
• Exposure to scripting languages for automation

Preferred Experience

Benefits

Skills Required

Fpga, RTL Coding, FPGA Design, systemverilog, Static Timing Analysis