What You ll Need :
- BTech / MTech in Electrical Engineering or related field.
- Minimum of 3 years of experience with MTech or 5 years with BTech in CMOS circuit design and layout methodology.
- Strong knowledge of deep submicron process technologies and CMOS processes.
- Familiarity with JEDEC requirements for DDR interfaces and standards.
- Experience with ASIC design flow and ESD concepts is an advantage.
Skills Required
ASIC Testing, ASIC Design, Ddr, Esd, CMOS