Layout Designer [Apply in 3 Minutes]

This is Jr position., If you are meeting with below criteria means pls share your resume to karthik.ravichandran@hays.com.au with below details..

• Over all experience;
• Relevant experience;
• CCTC;
• ECTC;
• Current location;
• Will you able to attend final round in F2F at Bangalore;

Location; Bangalore

Role; Custom Standard Cell Design Engineer

Final round must be F2F.

Job Description

You will be responsible for the development of Arm custom standard cells in the latest, sub-3nm process technology nodes. You will work as part of a team that co-optimizes the circuit design with physical design engineers to improve the PPA of Arm cores that will be integrated into best-in-class SoCs.

You will work in close collaboration with the mask design team to provide optimally tuned layout, characterize and model all standard libra

Required Skills and Experience :

An engineer with 1–4 years of experience in standard cell or custom circuit design, strong knowledge of CMOS device physics and transistor-level design, and hands-on expertise in SPICE simulation and cell characterization tools like Cadence Liberate or Synopsys SiliconSmart. Skilled in Python / Perl scripting, familiar with advanced process nodes (≤5nm), and capable of PPA optimization through close collaboration with layout and physical design teams.