Analog Modeling,Verification and characterization Senior Lead Engineer

General Summary :

Join Qualcomm's Hardware Engineering team where innovation meets silicon. In this role, you will contribute to the design and characterization of advanced mixed-signal IPs such as DDRIOs, SERDES, ADCs, DACs, and PLLs. This position focuses on developing Verilog behavioral models and performing accurate timing and power characterization using industry-standard tools. You'll be collaborating with cross-functional teams to ensure high-quality deliverables for Qualcomm's world-class chipsets.

Key Responsibilities :

• Develop behavioral models (Verilog, Verilog-MS / real, SystemVerilog) for mixed-signal analog IPs such as DDR-MSIP, DDRIOs, SERDES, ADC / DACs, and PLLs.
• Perform timing and power characterization using tools like Silicon Smart, HSPICE, FineSim, and NanoSim.
• Create Liberty (.lib) timing and power models and validate them against transistor-level designs.
• Develop and maintain self-checking testbenches and test plans for model verification.
• Conduct functional analysis and verification of modeled IPs using simulators like VCS.
• Collaborate with AMS teams for analog-digital interface verification and ensure robust modeling practices.
• Automate model generation and verification workflows using Tcl, Perl, or Skill scripting.
• Interface with design and verification teams to ensure model accuracy and completeness.

Minimum Qualifications :

Required Skills & Experience :

Skills Required

Hspice