Design Verification HBM Protocol

Job Title : Design Verification Engineer – HBM / Memory Controller

Location : Bengaluru / Hyderabad

Experience : 6+ Years

Role Overview

We are looking for an experienced Design Verification Engineer with strong expertise in HBM Protocol , Memory Controller Functional Validation , and Performance Verification . The engineer will contribute to test development, debug, coverage closure, and regression management for next-generation HBM (High Bandwidth Memory) subsystems.

Key Responsibilities

1. Functional & Performance Validation – Memory Controller (HBM)

End-to-end functional and performance validation of HBM-based memory controller IP / Sub-system.

Development of test content for both functional and performance scenarios.

Execution of test plans, test runs, waveform debug, and issue isolation.

Handling regression setup , tracking failures, triaging issues, and driving closure.

Coverage planning, coding, reporting, and analysis (Functional & Code Coverage).

Root-cause analysis and collaboration with RTL, architecture, and firmware teams for bug resolution.

Required Technical Skills

• HBM / Memory Expertise

Strong hands-on experience with HBM (HBM2 / HBM2E / HBM3) protocols.

Understanding of memory controller architecture, DFI, PHY interactions.

Experience verifying high-speed memory interfaces.

Solid experience in SystemVerilog for DV.

Expertise in UVM Verification methodology .

Testbench architecture, stimulus generation, scoreboard, functional coverage.

Experience with Assertion-Based Verification (SVA) .

Strong debugging using waveforms (e.g., Simvision, DVE, Verdi).

Failure triaging and RCA for functional and performance issues.

Regression execution and debug in simulation environments.

Experience with industry-standard verification tools :

Synopsys : VCS, Verdi

Cadence : Incisive / Xcelium, Simvision

Mentor / Siemens : Questa / Modelsim

Coverage tools, code coverage, functional coverage, assertion coverage.