Senior engineer-stdcells layout

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

• Design and maintain standard cells layout for new DRAM products on new technology
• Lead the stdcells layout projects from initial spec definition to till PPA qualified library release
• Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies
• Perform layout verification like LVS / DRC / Latchup, quality check and documentation.
• Responsible for on-time delivery of block-level layouts with acceptable quality.
• Demonstrate leadership Skill in planning, area / time estimation, scheduling, delegation and execution to meet project schedule / milestones in multiple project environment.
• Guide junior team-members in their execution of Sub block-level layouts & review their work.
• Contribute to effective project-management.
• Develop new flows / methodologies to reduce the stdcells manual effort & increase the productivity
• Closely work with the Process team, CMOS and CAD to negotiate drc for new technology.
• Co-work with international colleagues on developing new flows and tools for stdcells layout & design