Our organization is seeking talented hardware engineers to collaborate with frontier lab researchers.
- Develop realistic RTL design and verification problems that mirror industry complexity and best practices.
Key Responsibilities :
Build and optimize containerized environments for agent training tasks in hardware design workflows.Work directly with AI researchers to understand agent capabilities and training requirements.Requirements :
2+ years of experience in RTL design using Verilog / SystemVerilog or VHDL.Strong background in verification methodologies (UVM, SystemVerilog, testbench development).Experience with synthesis, timing analysis, and debugging tools.Familiarity with industry-standard EDA tools (Synopsys, Cadence, Mentor Graphics).Preferred Qualifications :
Strong problem-solving and analytical thinking skills.Excellent communication skills for cross-functional collaboration.Curiosity about AI / ML applications in hardware design.Ability to work independently in a remote environment.This position offers the opportunity to contribute to groundbreaking research in hardware design and AI. We welcome applicants who are passionate about innovation and collaboration.