Lead Engineer - Verification

Job description

The position involves design verification of next generation modem sub systems (which has MAC, Baseband and RF IP s involved for latest Wi-Fi protocol including 11ax) with emphasis on verifying and signing off performance and power along with functionality. This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, GLS and Formal techniques. Candidate will require close interactions with Design, SoC , Validation, Synthesis & PD teams for design convergence. Candidate must be able to take ownership of IP / Block / SS verification. He / She will work with design team (both HW and SW) on RTL debug during Pre-silicon HW development phase.

Responsibilities :

• Develop and track execution of chip level test planning to meet product requirements and established quality standards
• Lead a team to complete the pre-silicon verification of an SoC
• Execute and maintain chip level verification regressions. Triage and debug failing tests.
• Develop or update tests to satisfy the test plan requirements. Tests will be combination of directed (C tests), constrained random (UVM), and formal verification.
• Perform gate level verification across corners. Provide appropriate activity files for power analysis.
• Coordinate verification activities with a global team and the design lead. Provide succinct weekly status and drive action items to closure.

Experience Level  :   6-8 years in Industry

Education Requirements  :   Bachelor or Master s degree in Electrical and / or Computer Engineering

Minimum Qualifications :

Preferred Qualifications :

Skills Required

Java, Python, C++