Senior RTL Design Engineer

Company Description

A fast-growing, well-funded Silicon Valley deep-tech company building next-generation AI infrastructure and high-performance networking silicon . The company is pioneering breakthroughs in AI networking, data-center scale architectures, and custom ASIC solutions to eliminate system bottlenecks and dramatically improve performance of large-scale AI workloads.

Backed by seasoned industry leaders and world-class engineering talent, the team is redefining how modern AI data centers are built and scaled.

Senior RTL Designer – Networking ASICs (AI Infrastructure)

Shape the future of AI Networking by building next-generation, high-performance Networking ASICs .

🔷 What You’ll Do :

• Design high-speed packet buffering, queuing & scheduling architectures
• Optimize low-latency, high-throughput pipelines
• Work on on-chip memory subsystems and arbitration logic
• Implement & validate ASIC designs with verification teams
• Support cutting-edge protocols : Ethernet, IP & UCIe

🔷 What We’re Looking For :

✅ 8–15 years of RTL design experience

✅ Strong hands-on expertise in SystemVerilog / Verilog

✅ Proven experience in QoS & scheduling mechanisms

✅ Solid understanding of ASIC design flow

🌍 Location : Bangalore

📩 Apply / Refer : simon@ci-mc.com

Be part of a team building the backbone of next-generation AI systems.