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SoC RTL Design Lead
SoC RTL Design LeadTexas Instruments • India
SoC RTL Design Lead

SoC RTL Design Lead

Texas Instruments • India
8 hours ago
Job description

We are looking for an experienced Senior RTL Design Lead to join our team in developing cutting-edge control solutions and Application specific SoC products. The ideal candidate will have deep understanding of RTL design and SoC integration, particularly in the context of ARM-based architectures, and a proven ability to collaborate across multiple engineering disciplines to deliver high-quality solutions for complex systems.

Key Responsibilities :

  • Define and develop microarchitecture for various subsystems, including CPU subsystems, low-power subsystems, and Reset & Clock Management modules.
  • Drive SoC integration for motor control MCUs, ensuring efficient, scalable designs.
  • Collaborate with IP teams, Systems, and Architecture teams to derive requirements, co-develop microarchitecture, and align on design goals for IPs, subsystems, and SoC.
  • Work closely with cross-functional teams such as Design Verification (DV), Design for Testability (DFT), Emulation, and Physical Implementation to ensure quality deliverables.
  • Lead debug sessions, participate in design reviews, and ensure design robustness and compliance with industry standards.

Preferred qualifications :

  • Experience : Minimum 5+ Yrs SoC Digital Design.
  • Proficient in SoC toplevel RTL integration. As top level owner, has expereince working with cross functional domain owners – DV, Physical Design, Firmware, System Architects to collate requirements, plan deliverables and deliver RTL releases in timely manner
  • Experience with SoCs with ARM based CPU Subsystem integration (M0 / M33)
  • Experience with mixed signals designs with Analog integration – ADC, Osc, LDO etc. is a plus
  • Familiar with design of IPs and peripherals used in Generic MCU type of devices – DMA, Timers, Serial interfaces like SPI, UART, I2C etc.
  • Expertise in industry-standard front-end tools and flows such as Lint, CDC, LEC and power estimation tools - Jasper Gold, Litmus, Conformal, Joules etc.
  • Experience with industry standard simulators - (e.g. Xcelium, Simvision.), Formal verification tools
  • Experience with development of SDC timing constraints, Synthesis, LEC. Design for area and power optimization
  • Experience leading RTL design teams on an SoC – Digital Lead / Chip lead is a plus. Digital execution task planning and tracking.
  • Good understanding of DFT concepts and DFT architecture for SoCs
  • Good understanding of Physical design concepts – Flooplanning, IO Ring, Power plan, CTS, STA etc. is a plus.
  • Knowledge of scripting languages such as Python, Perl, or TCL for automation.
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