Design Verification Technical Manager

Experience Level : 20+ years of industry exp, with at least 5+ years in team management

Key Responsibilities :

We are hiring for candidate needs to have a hands-on experience with SV, UVM. Should have exposure to different verification methodologies and flows at IP, Sub System or SoC Level. Power Aware verification exposure, GLS verification exp is a plus. Lead and manage a team of highly motivated design verification engineers, providing technical guidance, mentorship and team management.

Qualifications & Experience :

Bachelor's / Master's degree in Electrical / Electronics / Instrumentation / Computer Engineering, or related fields from an institute of repute.

20+ years of industry experience.

Strong hands-on experience in TB design, test plan creation. Proficiency in verification flows, methodologies and languages such as System Verilog & UVM.