Design Verification Engineer

Responsibilities

Collaborate with designers, architects, and verification teams to verify the design, architecture, and micro-architecture of ASICs. This includes developing the verification infrastructure, defining the verification scope, and using advanced verification methodologies.

Skills

Use computer hardware languages like Verilog, and have experience with FPGA design, LLVM, HLS, DDR Memory, and MATLAB. You should also be comfortable with emulation, regression testing, and algorithm design

Experience : 5+yrs

Notice period : Immediate - 45days