Senior STA Engineer

Large Semiconductor Service Organization with revenue over 600 Million USD

Location : Bangalore

STA Lead

Experience : 7+ Years

Work location : Bangalore

• Well versed with the timing closure (STA), timing closure methodologies.
• Pre / Post-layout constraint development to timing closure.
• Handshake with the design team and develop functional / DFT constraints.
• IP level constraint integration.
• Multi-voltage / Switching aware corner definitions.
• RC / C model selection understanding.
• Abstraction expertise like Hyperscale / ILM / ETM.
• RC Balancing and scaling analysis of full chip clock.
• RC Balancing and scaling analysis of critical data paths.
• Good automation skills in PERL, TCL and EDA tool-specific scripting.
• DMSA @ full chip and custom scripts for timing fixes

Qualification :

2 - STA Engineer.

Contact : Uday

Mulya Technologies

muday_bhaskar@yahoo.com

"Mining The Knowledge Community"